This invention relates to integrated circuit (IC) chip test software systems and more particularly to refining logic bitmap using pruned diagnostic list.
Digital semiconductor integrated circuits are manufactured on dies of a silicon wafer. There are both memory chips and logic chips. A microprocessor chip is an example of a logic chip. A field known as Design for Test (DFT) involves designing into the chip xe2x80x9cscan chainsxe2x80x9d that are used to write and read portions of the chip that might be otherwise inaccessible. Layout tools are used to lay out a chip design onto the silicon wafer. The chip layout may be represented in the form of a netlist which is a bit of low-level design cells and the interconnections between them. Once the design is completed, the bits of a file representing the chip are written to a tape or disk. A mask maker makes photomasks to manufacture the chip using the files.
The chips are production monitored and tested. Production monitoring is performed using xe2x80x9cin-linexe2x80x9d inspection equipment and production testing is performed using xe2x80x9cend-of-linexe2x80x9d test equipment. In-line inspection equipment inspects the entire semiconductor wafer, each of which may have hundreds of chips. The end-of-line test equipment performs what is called xe2x80x9cbinsort function testxe2x80x9d on the semiconductor wafers wherein the pads of the chip are contacted by test equipment and the chips are operated. At the conclusion of the test, parts are xe2x80x9cbinnedxe2x80x9d or placed in different categories within an electronic record according to test result. The categories relate to the quality of the chip (bad, good, high quality, etc.).
Failure analysis attempts to identify the cause of failure of chips of a particular chip design after the failures have been detected during production or prototype testing. Failure analysis usually requires more detailed failure information than just a bin code. Detailed failure information is typically obtained by re-testing a number of packaged parts.
Memory chips in reality lend themselves to failure analysis because of their structure as regular arrays of memory cells. A memory chip may be tested by a series of read and write questions to the memory chip. The errors in read/write testing pin-point likely physical defects at readily identified location. Alternatively, the memory chip can have built in self test (BIST) capabilities. The functional test results can be xe2x80x9cbitmappedxe2x80x9d to failure locations on the memory chip. In memory bitmapping, electrical failures are realized within relatively small physical xe2x80x9ctracexe2x80x9d on the die.
FIG. 1 illustrates the process flow with conventional bitmap testing wherein the wafer undergoes in-line inspection (right column) and end-of-line testing (left-hand column). This in-line testing may be done using optical test equipment like KLA21xx from KLA Tencor to produce defect files containing X, Y location defect information. End-of-line testing is performed by Automatic Test Equipment (ATE), which identifies failed memory locations. This is processed to identify X, Y defect locations. The X, Y defect information may be output to a Yield Manager tool. Because these are in the same format within the Yield Manager tool, a combined defect overlay is obtained to determine xe2x80x9ckiller defectsxe2x80x9d or defects that render a part non-functional to be identified. The locations of a defect and a failure coincide. As a result of this identification, trouble-shooting would focus on the production process rather than the design of the part.
In recent years, the market share of logic products has increased with many new xe2x80x9clogic onlyxe2x80x9d semiconductor fabs without the benefit of a xe2x80x9cmemory production line to monitor the production process and take advantage of the yield enhancement technique developed within the industry.xe2x80x9d There has been no way to xe2x80x9cbitmapxe2x80x9d area of logic within a chip. Furthermore, logic chip function test results do not provide a starting point for the physical coordinates of failures within a failed die.
The most advanced logic chip designs contain scan testing. Scan testing breaks the logic real estate of a chip into many discrete chains of logic which can be tested individually for basic functionality. Scan testing enables a list of failing signals to be identified. However, even after a list of failing signals is produced for a given dies, it is still not possible to find the physical location of the failure because each failing signal may contain hundreds of transistors within its xe2x80x9ccone of logic,xe2x80x9d and there are usually multiple failing signals. Traditional logic chip yield enhancement techniques therefore rely heavily on correlation of binsort functional test results to anticipate and correct semiconductor process issues. This approach suffers from several drawbacks, including: the inability to relate a particular bin""s fall-out to a suspect process level; the inability to distinguish pre-packaging yield issue from packaging yield issues; and the inability to establish a clear link between large populations of failed die.
Failure analysis may make use of a known electrical diagnosis process whereby a diagnostic list of suspected failing nets may be obtained as shown in FIG. 2. Packaged devices having BIST (scan) capabilities are tested using a tester. Scan failure data is translated into format that can be used by an ATPG (Automatic Test Pattern Generation) tool, e.g., an ATPG tool used previously to generate test pattern files used by the tester. The ATPG tools use the translated test data, together with the test pattern files, setup files, one or more ATPG diagnostic models, and design information from a design database in order to identify suspected failing nodes, output in the form of a diagnostic list (FIG. 3).
CAD navigation tools have been developed to aid in failure analysis. CAD navigation refers to the ability to point and click within a circuit layout display and by so doing automatically drive a piece of equipment such as FIB (Focussed Ion Beam) equipment to that location on the chip. CAD navigation also allows a user to specify the name of a net, causing the corresponding layout to be displayed. Once such CAD navigation tool is the Merlin Framework CAD navigation tool of Knights Technology. This tool takes netlist information, layout information, and cross-reference files relating the two and procedures a unified database in a Knights-proprietary format having an efficient indexing structure. Referring more particularly to FIG. 4, the process of creating such a Knights database is illustrated in greater detail. A SPICE-formatted netlist is converted (if required) to a suitable netlist format. Data from a Schematic Verification database is converted (if required) to obtain cross-reference files cross-referencing net names and numerical net identifiers. Layout data is converted (if required) to a suitable polygon layout format. An MMapper routine uses the netlist, cross-reference files and polygon layout files in the following manner to produce a database suitable for CAD navigation.
In a co-pending application Ser. No. 09/192,164 filed Nov. 13, 1998 (now U.S. Pat. No. 6,185,707B1), of Shawn Smith, Han Balachandran and Jason Parker entitled, xe2x80x9cIC Test Software System for Mapping Logical Functional Test Data of Logic Integrated Circuits to Physical Representation,xe2x80x9d incorporated herein by reference, takes advantage of the foregoing capability to determine and display the X,Y location corresponding to a net name, by translating functional test data of a digital logic chip passed through a simulation model which identifies one or more defective nets of the chip. The defective nets are processed against a database of the type to obtain X, Y coordinate data for these nets, allowing them to be data tagged as physical traces on the chip layout. The mapping is performed by taking the output from a functional tester and translating it form a list of failed scan chains into a list of suspected netlist nodes. The X, Y coordinates of suspected netlist nodes are then identified and stored in a database, providing failure analysis and yield enhancement engineers a starting point for performing failure analysis and for understanding whether xe2x80x9cin-linexe2x80x9d inspection data can account for a given failure.
Presently, logic bitmap is performed using a stuck-at fault list. In a stuck-at fault testing model, various nets of the circuit are tested by applying patterns of values inserted via the scan cells to determine if appropriate voltage values are obtained at the nets. For example, if a series of values is applied to the scan cells within the circuit such that the voltage value at a particular net should be at a high voltage level, but the voltage level at the particular net remains at a low voltage level, a stuck-at fault is detected. Given information about a particular circuit""s design, manufacture, and logic flow, a stuck-at fault dictionary can be generated containing entries for each particular net that shows how the circuit would respond in the presence of those stuck-at-faults. Such flaws may include, but are not limited to, pin faults, element failures, metallization failures, improper metal oxidation, or incorrect ion implantation.
However, not all problems in a circuit can be detected using stuck-at fault testing models. Stuck-at fault models may not present a design or manufacturing team with sufficient information to easily determine the causes of particular faults that are detected in a circuit. Other faults, known as bridging faults, include faults that are the result of defects or failures involving more than one particular net. For example, two metal leads within a particular circuit layer or in adjacent circuit layers may be shorted, causing a fault that may not be easily detected or diagnosed using a stuck-at fault model of testing. The problem with this methodology is that the confidence level of the stuck-at diagnostic tools is only between fifty and seventy percent.
In accordance with one embodiment of the present invention, the net/node information given by the bridging/stuck-at diagnostic tools is combined with the susceptible bridging candidates extracted from the layout information. The bridging candidate extraction needs to be performed only on those nets reported by the diagnosis tool. A pruned bridging and stuck-at diagnostic list is then used to perform defect matching.